1. Field
This invention relates to non-volatile electronic counters in integrated circuits, more specifically, a counter which can store volatile digital data in a non-volatile register prior to power outage and can recall the data following the power outage.
2. General Background
Non-volatile counters implemented in integrated circuits typically consist of a volatile counter that has the capability of transferring its contents to a non-volatile register prior to power being removed. When power is restored, the contents of the non-volatile register (retained during the power off condition) are transferred back into the volatile counter and counting can continue where it ended prior to the disruption of power. This integrated circuit configuration is typically implemented with (i) binary volatile counter well known in the industry and (ii) one or more non-volatile registers (referred to as a "latch circuit") as set forth in U.S. Pat. No. 4,571,704.
This latch circuit configuration is complex to design and occupies a large amount of area when implemented in an integrated circuit. For example, the latch circuit requires two non-volatile transistors to store its logic state during the power off condition, one for each side of the latch circuit. Often, since the non-volatile memory elements have a limited lifetime, two non-volatile transistors are used for each side of the latch circuit to provide more reliable operation through redundancy. Since the non-volatile transistors used in the latch circuit are all relatively large, the use of four non-volatile transistors to store one bit of data is an inefficient use of area in the integrated circuit and results in a high implementation cost.
There are also reliability concerns for this implementation. Under conventional memory designs, non-volatile transistors placed in a parallel redundant manner are tested in a collective manner by monitoring a voltage level at a shared node. These transistors cannot be tested independently after manufacture. One difficulty is that that non-volatile transistors typically reside in an "open" or non-conducting state upon failure. Therefore, if one of the transistors has failed and no redundancy is present, the testing may still reveal that the latch circuit is operating properly. This has an effect on long term reliability of the non-volatile counters.
Also, a general reliability problem in non-volatile counters is that the volatile counter is typically coded in binary, where the least significant bits change state substantially more often than the most significant bits in the counter. Therefore, when information in the counter is transferred into the non-volatile latches, the latches receiving the least significant bits change state more often than those receiving the more significant bits. As a result, the latches responsible for storing the least significant bit of the volatile counter will normally fail well before latches associated with the other bits. In many situations, the volatile counter is implemented in a binary coded decimal configuration (a decimal configuration, with each decimal coded in binary and often referred to as a "BCD" configuration) rather than a straight binary counter. The reliability problem is the same for this configuration, as the least significant bits of each decimal stage change state in a binary fashion and the lower order decimal stages change state more often than the higher order stages.